1. Field of the Invention
The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device that includes a plurality of internal circuits belonging to a plurality of power supply systems that are separated and independent from each other, respectively, and further includes a electrostatic discharge (ESD) protection circuit used to protect interface circuits located between the plurality of internal circuits belonging to the plurality of power supply systems, respectively, from an ESD-originated surge current.
2. Background Information
A semiconductor device has been known which has a plurality of internal circuits belonging to a plurality of power supply systems that are separated and independent from each other, respectively. The plurality of internal circuits are electrically coupled to each other through interface circuits. For example, a signal that is output from an internal circuit belonging to a power supply system is input into another internal circuit belonging to another power supply system through an interface circuit. The interface circuit can be typically comprised of a complementary metal oxide semiconductor (CMOS) inverter circuit.
Each of the internal circuits belonging to each of the power supply systems is comprised of at least a high potential side power supply terminal and at least a low potential side power supply terminal. In other words, each of the plurality of power supply systems that are separated and independent from each other is comprised of at least a high potential side power supply terminal and at least a low potential side power supply terminal. Therefore, a semiconductor device is comprised of at least a high potential side power supply terminal and a low potential side power supply terminal, and the number of terminals which are the same as or greater than the number of the power supply systems. The term “power supply terminal” hereinafter includes not only a high potential side power supply terminal and a low potential side power supply terminal, but a terminal in a path providing power to the circuit.
ESD-originated surge current can be applied to any of the plurality of power supply terminals in the semiconductor device. Therefore, even when surge current is applied to any of the power supply terminals, the ESD protection circuit has to protect each of the interface circuits from surge current.
Japan Patent Application Publication JP-A-09-172146 discloses a semiconductor device in which an ESD protection circuit is provided for an interface circuit located between an analog circuit belonging to a first power supply system and a digital circuit belonging to a second power supply system (especially paragraphs 0010 to 0012, and FIG. 1). The ESD protection circuit is provided for every interface circuit. More specifically, one ESD protection circuit is provided between two CMOS inverter circuits. In general, a semiconductor device has a plurality of interface circuits. Therefore, a semiconductor device has a plurality of ESD protection circuits corresponding to the plurality of interface circuits, respectively.
According to the conventional circuit configuration, ESD protection circuits are required, with the number thereof being the same as the number of the plurality of interface circuits belonging to a power supply system. For example, an interface having logic gate circuits, the number of which is the same as the bit number of a digital signal, can be used for transmitting a digital signal between two internal circuits belonging to power supply systems that are separated and independent from each other, respectively. According to this type of circuit configuration, the increasing number of interface circuits is caused by the increasing bit number of a digital signal, and the increasing number of ESD protection circuits is caused by the increasing number of interface circuits. Furthermore, the area occupied by the plurality of ESD protection circuits will be increased. This makes it difficult to reduce the size of and miniaturize a semiconductor integrated circuit (a semiconductor IC) comprising a semiconductor device.
Therefore, there is a demand for a reduction in the total area occupied by the ESD protection circuit without depending on the bit number of a signal, that is, the number of interface circuits.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved semiconductor device. This invention addressed this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.